The big change in the code from the users point of view is the addition of a new recording mode. Mode 3. In this mode the ADC converters are running in burst mode. Once they complete one conversion they immediately start another one. A list of input channels is scanned for the next channel to use and once the list is finished, it starts over at the beginning again. Completion of a conversion triggers an interrupt and the interrupt routine reads the result and buffers it for writing to the SD card. The main reason for adding this mode was to eliminate all of the time wasted polling the ADC to see if it was done with a conversion. While it was doing that the file system code could not run.
Three new parameters are added to the configuration file and they are all about the clocks. The ADC's run from a clock derived from the main CPU clock and the range of possible divisors is 1 to 256. The lower values may not work if they result in an ADC clock greater than 4.5 MHz. Each ADC will complete a conversion once every 11 ADC clocks.
The conversion rate set by the clock is the total and if more than one channel is enabled then the per channel rate drops accordingly. If the ADC conversion rate is 10,000 SPS then if only one channel is enabled then it will be sampled at 10,000 SPS. But if five channels are enabled then each will be sampled at 2,000 SPS.
Each converter has its own clock divider value so they can run at different rates.
The third additional parameter (pllM) changes the CPU clock. With the default clock of 58.9824 MHz the slowest the ADC's will run at is about 21,000 SPS. This may be much more than is needed. Lowering the CPU clock decreases this and also results in lower power consumption. There are only three options for this setting: 1 results in a clock rate of 14.7456 MHz, 2 in 29.4912 MHz and 3 in 44.2368 MHz.
The lower clock rate may also place a lower limit on the SD write speed so be sure to verify that data is not being dropped.
With pllM set to 1, the ADC 0 divisor at 100, the ADC 1 divisor at 256, one ADC 0 channel enabled and all six ADC 1 channels enabled produces the following sample rates:
|ADC 0||13,405 SPS|
|ADC 1||872.7 SPS (per channel)|
Data will be written to the SD card at ~37KB/sec.
When the result of each ADC conversion is recorded the 10 bit result is stored in a 16 bit word. Since the upper six bits were doing nothing I decided to record the ADC and channel number that produced the result there. The most significant bit is 0 for ADC 0 and 1 for ADC 1. The next 3 bits encode the channel number and the two remaining bits are set to zero. This channel information is used to demultiplex the data.
A 16 byte header is recorded ahead of the actual ADC data. Most of this is empty right now but it includes the mode, number of channels on each ADC enabled, and the clock divider values. This allows the simple program that processes the data file to add a time value.
A simple program reads the data file and creates an output file for each enabled channel. The data is in two columns with the first being the time and the second being the ADC result with a range of 0 to 1023. Further processing into engineering units is up to the user.
The time defaults to being in seconds but if the '-c' option is given this is in CPU clock cycles. Simply dividing by the CPU clock provides time.
The other option is '-p prefix' which changes the default output file from "DATAxxxxx" to "prefixxxxx". This program makes no attempt to keep from destroying files that already exist. If the name matches it will be replaced so be sure to use unique prefixes.
Be sure to have lots of free disk space as the very large files can eat it up in a hurry. The number of data points is hard to work with and you may need to split the files up into more manageable chunks using a program like 'split'.
gnuplot made a good effort at reading in a 600MB+ file but eventually ran out of memory. I knew I should have created a bigger swap partition.